The invention generally concerns the high-temperature treatments carried out on multilayer semiconductor wafers such as e.g. silicon-on-insulator (SOI) wafers.
The invention can thus be used for treating SOI wafers, but it also applies to any kind of multilayer wafer made with materials selected from the semiconductor materials (“semiconductor wafers”).
In this text the “high temperatures” (HT) refer to temperatures of at least 800° C., while the term “transfer method” refers to a method for manufacturing multilayer semiconductor wafers, and implying a transfer step during which:                a top (or “donor”) wafer is bonded on a base wafer (also called “handle”, or “receiver” wafer),        at least part of the top wafer remains with the base wafer after the bonding.        
A transfer method can be carried out e.g. according to the following methods:                the Smart-Cut® method (it is specified that a general description of this method can be found e.g. in Jean-Pierre Colinge—“Silicon On Insulator Technologies, Materials to VLSI”, Kluwer Academic Publisher, 2nd edition),        the ELTRAN™ method, or        other layer transfer methods.        
The “active layer” of a multilayer semiconductor wafer is the layer in which components shall be created—this layer being generally electrically isolated from the rest of the wafer. The active layer is generally a surface layer of the wafer. The Dit is the parameter which characterizes the trap interface density—which is defined as the density of electrical traps located at an interface between two layers of a multilayer structure. It is specified that in this text Dit and “trap interface density” are understood as equivalent.
This density is generally expressed in count of traps per (eV.cm2)—i.e. in #/eV.cm2—and typical values for the interface BOX/active layer in a SOI are 1012 #/eV.cm2. Dit can be measured using e.g. pseudo MOSFET measurement techniques.
In the case of a multilayer wafer having an active layer on top of a buried insulating layer, “the Dit” of the wafer shall in this text refer to the Dit at the interface between the buried insulating and the active layer of the wafer. For e.g., a SOI-type wafer, the Dit of the wafer thus refers to the Dit at the interface between the surface active layer and the buried oxide insulating layer (BOX).
It is specified that in this text we shall refer to “SOI-type wafers” as multilayer wafers comprising:                a support layer (e.g. bulk Si for a classical SOI),        an active layer located in the surface region of the wafer (e.g. a thin film of Si—but possibly other types of films such as SiGe, Ge, or others), and        a buried insulating layer between these two layers (e.g. a buried oxide layer).        
Dit is an important parameter since it has an influence on the mobility of electrical carriers in the layers of the multilayer wafer. As an example, Dit at a BOX/active layer interface of a SOI has an influence on the carrier mobility of the active layer—the carrier mobility being in turn a parameter which influences the electrical performance of the wafer.
It is thus desired to control the value of the Dit of a multilayer wafer (i.e. at the interface BOX/active layer for a SOI wafer), in order to influence the electrical performance of the wafer (and the performance of the devices that will be formed on the wafer).
More precisely, in the perspective of increasing the mobility of electrical carriers in the active layer of a multilayer semiconductor wafer, it can be desired to minimize the value of the Dit of the wafer (it has been shown that a lower Dit of the wafer is associated with a higher mobility). In the case of a typical SOI wafer comprising an active layer (e.g. in Si) covering an insulating layer (e.g. an oxide layer), this would mean that it is desired to reduce the Dit at the interface between the active layer and the oxide layer.
High temperature annealing steps used for fabricating SOI-type wafers (e.g. SOI wafers) may require the use of “low slip lines” SiC boats with large surface of contact between the wafer and the boat, in order to minimize slip line generation. However, it has been observed that the use of such boats is associated with another drawback under the form of defects associated to a tearing-off (“tearing-off defects”) on at least one layer of wafers which have undergone a HT treatment in such a boat.
To avoid the generation of such tearing-off defects, it is possible to reduce the value of the boat-in temperature (i.e. the temperature at which the wafers are introduced in the annealing chamber). Reducing the boat-in temperature indeed allows to reduce the thermal induced mechanical stress during the transition between ambient temperature and idle temperature of the annealing chamber. And a reduced boat-in temperature furthermore allows a reduction of particle contaminants on the wafers treated in an annealing chamber.
It is specified that in a context of industrial exploitation, the boat-in temperature of a thermal treatment is substantially equal to its boat-out temperature (temperature at which the wafers are put out of the annealing chamber). This equality between boat-in and boat-out temperatures is indeed a basic and natural disposition which allows to limit the time between the annealing of two successive batches of wafers, and thereby limit time where the annealing chamber is not used effectively.
Tests have been conducted for HT treatments on SOI-type wafers, with a reduced boat-in (and thus boat-out) temperatures. These tests were conducted so as to adapt a typical HT treatment of a SOI obtained by a transfer method such as e.g. the SMART-CUT® method.
Such typical HT treatment is usually carried out with the following steps:                A first phase includes a transient phase of temperature stabilization at (or around) boat-in temperature, after the introduction in the chamber of a “cold” element at a boat-in temperature of about 600° C., and a first ramp up,        A second phase corresponds to a thermal oxidation carried out between 800° C. and 1000° C. (e.g. around 950° C.). This phase is carried out under an atmosphere containing oxygen,        A third phase called stabilization phase, is carried out between 900° C. and 1200° C. (e.g. around 1100° C.). This phase aims in particular at stabilizing a bonding interface between two layers of the wafer.        A final step includes a temperature ramp-down and boat out, at the same temperature as boat in.        
For the tests conducted, the boat in and boat-out temperatures were lowered to 450° C., instead of 600° C. The rest of the “typical” HT thermal treatment described above was unchanged. It was unexpectedly discovered that lowering the values of boat-in/boat-out temperatures from 600° C. to 450° C. avoided generating tearing-off defects. However, such reduction was associated with another drawback.
It has also been observed that the value of the Dit of the wafers which had undergone the test mentioned above was significantly increased. This increase of Dit is illustrated in FIG. 1, which shows the values of Dit for two respective sets of batches of SOI wafers which have been respectively annealed according to:                a “typical” HT treatment such as mentioned above (boat-in/boat-out at 600° C.)—this corresponds to the left-hand part of FIG. 1, illustrating the Dit observed for a first set of batches (“set 1”),        the tests mentioned above (boat-in/boat-out at 450° C.)—this corresponds to the right-hand part of FIG. 1, illustrating the Dit observed for a second set of batches (“set 2”).        
Thus, the increased Dit observed when lowering the boat-in/boat-out temperatures of the HT treatment mentioned above corresponds to a drawback.
A goal of the invention is to eliminate—or at least diminish as much as possible this drawback in order to provide enhanced properties to the wafer by the annealing process.